n-stage shift register - translation to English
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n-stage shift register - translation to English

CASCADE OF FLIP-FLOPS SHARING THE SAME CLOCK, IN WHICH THE OUTPUT OF EACH FLIP-FLOP IS CONNECTED TO THE INPUT OF THE NEXT FLIP-FLOP IN THE CHAIN, RESULTING IN A CIRCUIT THAT SHIFTS BY ONE POSITION THE BIT ARRAY STORED IN IT
Shift registers; 74HC595; Shift Register; Shift-register
  • Toshiba TC4015BP{{snd}} dual 4-stage static shift register (with serial input/parallel output)

n-stage shift register      
n-ступенчатый сдвиговый регистр
linear feedback shift register         
  • A Fibonacci 31 bit linear feedback shift register with taps at positions 28 and 31, giving it a maximum cycle and period at this speed of nearly 6.7 years.
  • A 16-bit [[Fibonacci]] LFSR. The feedback tap numbers shown correspond to a primitive polynomial in the table, so the register cycles through the maximum number of 65535 states excluding the all-zeroes state. The state shown, 0xACE1 ([[hexadecimal]]) will be followed by 0x5670.
  • A 16-bit Galois LFSR. The register numbers above correspond to the same primitive polynomial as the Fibonacci example but are counted in reverse to the shifting direction. This register also cycles through the maximal number of 65535 states excluding the all-zeroes state. The state ACE1 hex shown will be followed by E270 hex.
TYPE OF SHIFT REGISTER IN COMPUTING
LFSR; Linear feedback shift registers; LSFR; Linear feedback register; Generalised feedback shift register; Polynomial counter; ALFSR; GFSR; Linear feedback shift register
сдвиговый регистр с линейной обратной связью
LFSR         
  • A Fibonacci 31 bit linear feedback shift register with taps at positions 28 and 31, giving it a maximum cycle and period at this speed of nearly 6.7 years.
  • A 16-bit [[Fibonacci]] LFSR. The feedback tap numbers shown correspond to a primitive polynomial in the table, so the register cycles through the maximum number of 65535 states excluding the all-zeroes state. The state shown, 0xACE1 ([[hexadecimal]]) will be followed by 0x5670.
  • A 16-bit Galois LFSR. The register numbers above correspond to the same primitive polynomial as the Fibonacci example but are counted in reverse to the shifting direction. This register also cycles through the maximal number of 65535 states excluding the all-zeroes state. The state ACE1 hex shown will be followed by E270 hex.
TYPE OF SHIFT REGISTER IN COMPUTING
LFSR; Linear feedback shift registers; LSFR; Linear feedback register; Generalised feedback shift register; Polynomial counter; ALFSR; GFSR; Linear feedback shift register
сокр. от linear feedback shift register
сдвиговый регистр с линейной обратной связью

Definition

ДИМЕТИЛФОРМАМИД
(CH3)2NCHO, бесцветная жидкость, tкип 153 °С. Растворитель в производстве синтетических волокон, красителей, при выделении ацетилена из газовых смесей.

Wikipedia

Shift register

A shift register is a type of digital circuit using a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this configuration they were used as computer memory, displacing delay-line memory systems in the late 1960s and early 1970s.

In most cases, several parallel shift registers would be used to build a larger memory pool known as a "bit array". Data was stored into the array and read back out in parallel, often as a computer word, while each bit was stored serially in the shift registers. There is an inherent trade-off in the design of bit arrays; putting more flip-flops in a row allows a single shifter to store more bits, but requires more clock cycles to push the data through all of the shifters before the data can be read back out again.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as "serial-in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also "bidirectional" shift registers, which allow shifting in both directions: L → R or R → L. The serial input and last output of a shift register can also be connected to create a "circular shift register". A PIPO register (parallel in, parallel out) is very fast – an output is given within a single clock pulse.

What is the Russian for n-stage shift register? Translation of &#39n-stage shift register&#39 to Rus